This invention relates to programmable logic devices. More particularly, this invention relates to dual-port programmable logic device variable depth and width memory arrays.
Programmable logic devices are integrated circuits that are programmable by a user to perform various logic functions. At their most basic level, programmable logic devices contain programmable components, such as erasable programmable read-only memory (EPROM) transistors, electrically erasable programmable read-only memory (EEPROM) transistors, random access memory (REM) transistors or cells, fuses, and antifuses. Higher-level functions are provided by organizing the programmable components into groups of components. The groups of components are electrically connected to one another by programmable interconnections. An illustrative programmable logic device is described in Cliff et al. U.S. Pat. No. 5,689,195.
Programmable logic devices such as those described in U.S. Pat. No. 5,689,195 generally have arrays of random-access memory (RAM) for storing data during device operation. The memory arrays, which are sometimes referred to as embedded array blocks (EABs), are made up of rows and columns of memory cells. The word size used to access data in the memory arrays is generally smaller than the physical dimensions of the memory arrays. For example, a two kilobit (2K) memory array might have 64 rows and 32 columns of memory cells for storing data, whereas the device might use eight-bit data words. When it is desired to read or write a data word, the eight data bits are either retrieved from or written to the memory array.
Memory arrays of this type may be provided with a variable depth and width feature that allows the size of the data word that is used to access the memory array (its xe2x80x9cwidthxe2x80x9d) and the resulting capacity of the array for data storage (its xe2x80x9cdepthxe2x80x9d) to be selectively programmed by the user. A typical 2K variable depth and width memory array can be programmed to have the respective depth and width configurations of: 2Kxc3x971, 1Kxc3x972, 512xc3x974, or 256xc3x978.
With such variable depth and width memory arrays, data may be either written to or read from the array in words of the selected width. However, these variable depth and width memory arrays do not permit the user to write data to the array and read data from the array simultaneously. Such a capability is needed for applications in which the memory array is used to implement a first-in-first-out buffer or in other such applications in which the memory array is shared between two concurrent processes, one of which reads data from the array and one of which write data to the array.
It is therefore an object of the present invention to provide a variable depth and width memory array for a programmable logic device in which data words may be written to the array and read from the array concurrently.
This and other objects of the invention are accomplished in accordance with the principles of the present invention by providing a dual-port variable depth and width programmable logic device memory array. Data may be written into a selected write location in the array via a first port with write column decoder and data selection logic and a write row address decoder. Data may be read out of a selected read location in the array via a second port with read column decoder and data selection logic and a read row address decoder. The write column decoder and data selection logic and the write row address decoder operate independently of the read column decoder and data selection logic and the read address decoder. Write operations may therefore be performed independently from read operations. This dual-port feature allows the memory array to be used to implement first-in-first-out buffers and other such memory configurations. The dual-port feature therefore facilitates certain types of data manipulation that would otherwise not be possible.
In an illustrative embodiment, the dual-port memory array handles data widths of 1, 2, 4, 8, and 16 bits. The sizes of the data words handled by the write column decoder and data selection logic are determined by mode select signals. The locations of the columns of the memory array that are addressed during a write operation are determined by write addresses. The number of bits of write column address information used by the write column decoder and data selection logic is determined by the size of the data words to be written to the array. Input registers may be used to register data words up to 16 bits in width prior to providing this data to the write column decoder and data selection logic.
The size of data words handled by the read column decoder and data selection logic are also determined by mode select signals. The locations of the columns of the memory array that are addressed during a read operation are determined by read addresses. The number of bits of read column address information used by the read column decoder and data selection logic is determined by the size of the data words to be read from the array. Output registers may be used to register data words from the array up to 16 bits in width prior to distributing this data on the programmable logic device.
Input multiplexers receive separate and independent read enable and write enable signals for the dual-port memory array that are distributed from interconnects on the programmable logic device. Control logic is used to process these read and write enable signals and to generate correspondingly separate and independent secondary write enable (WE) and read enable (RE) signals. The secondary write enable signal is used by the write row address decoder to address a given row of the array. The location of the row into which data is to be written is determined by a write row address supplied to the write row address decoder from the input multiplexers. The secondary read enable signal is used by the read row address decoder to address a given row of the array. The location of the row from which data is to be read is determined by a read row address supplied to the read row address decoder from the input multiplexers.
In general, the memory array location for writing that is specified by the columns identified by the write column address and the row defined by the write row address differs from the memory array location for reading that is specified by the columns identified by the read column address and the row defined by the read row address. Variable depth and width data words can therefore be written to the array and read from the array using concurrent processes, i.e., one process may write data while the other process reads data.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.